Akshay Mehta

Akshay Mehta

Senior undergraduate at IIT Kanpur

About me

I am currently a fourth year undergraduate from Indian Institute of Technology, Kanpur majoring in Electrical Engineering. I am interested in web development, machine learning and NLP.

Work Experience

  • Machine Learning Research Intern at UC San Diego, Design Lab
    • June 2022 - Present(Virtual)
    • Collect social media posts using python and R scripts that I created.
    • Develop a framework for collecting, preprocessing, and analyzing text from social media posts for research analysis that will be done in Professor Imani N.S. Munyaka’s lab.
    • Analyze social media posts using the latest techniques in natural language processing (sentiment analysis, N-grams, topic modeling, text networks)
    • Analyze social media posts using various python and Twitter APIs to provide descriptive statistics (bot detection, emoji counts, identify influencers)
    • Provided literature review on previous work related to summer research topic
      • Mini Project Reddit post comments analysis : Requires collecting comments from posts on Reddit and analyze the comments on reddit post using NLP techniques in python.

Projects

  • DARK ADDER
    • Mentor : Dr. Urbi Chatterjee, Department of Computer Science and Engineering, IIT Kanpur
    • Developed a digital Hardware Trojan Horse (HTH) that renders approximate adder circuit’s inefficiency
    • Exploited the probabilistic nature of approximate designs to successfully implant the Hardware Trojan Horse
    • The presented Hardware Trojan Horse replaces the original sum-bit generation logic in a 1-bit full adder widely present as a building block in a major class of block-based low latency approximate adders
    • Impact of a digital HTH may be mild in exact computing designs, but it alters the behaviour of approximate circuits in practical scenarios such as machine learning (K-means clustering) & image processing (Gaussian Smoothing)
    • Dark Adder : Digital Hardware Trojan Attacks on Block based adders by Vishesh Mishra, Neelofar Hassan, Akshay Mehta, and Dr. Urbi Chatterjee was accepted at The 36th International Conference on VLSI Design (VLSID 2023)
  • DESIGN LOGIC GATES
    • Course Project, VLSI System Design
    • Designed the 2-input NAND, NOR and XOR gate in complementary static CMOS logic using LTspice and Electric tools
    • Validated the design rule check (DRC) and the layout vs schematic (LVS) check for each and every gate

  • Audioband: Worked with 10 other IITK students, to assembled a wrist worn device to recognise hand gestures using ultrasonic beam forming and acoustic reflectometry under Electronics Club, IITK

  • Algorithms based on maths:Learned the programming techniques and their time complexity analysis such as Hashing, Modular multiplication inverse, Matrix Exponentiations, Dynamic Programming,etc. under Stamatics, IITK

  • Todos-Application and Linear_Regression are my self projects to get familar with the technologies.

I am Familiar with

  • Programming Languages : C, C++, Python, SQL, LATEX, Javascript
  • Libraries : Numpy, Pandas, Matplotlib, STL
  • Technologies : HTML, CSS

My Personal Interests

  • Chess, Table Tennis
  • Watching Web series & Movies .
  • Reading tech blogs.